As very-large-scale integration (VLSI) becomes a development trend of integrated circuits (ICs), the internal circuit density of ICs increases and the number of the components included in ICs also increases, and accordingly, the size of the components decreases. With the reduction of the size of semiconductor structures, the length of the channel of the devices in the semiconductor structures becomes shorter. Because of the reduction of the channel length, the gradient channel approximation is no longer valid, and various undesired physical effects (especially the short channel effect) become prominent, causing degradation of the performance and the reliability of the device and also limiting the further reduction of the size of the device.
As the circuit density increases, the wafer surface cannot provide enough area for the formation of the connection wires. After the components are reduced, in order to meet the interconnection requirements, the design of interconnections between multiple metal layers (i.e., two or more layers) has become one of the methods commonly used in the VLSI technology. The electrical connections between different metal layers and/or between each metal layer and the semiconductor device may be realized by a plurality of plugs.
In the meantime, the carrier mobility is one of the main factors that may affect the performance of a transistor. Effectively increasing the carrier mobility has become one of the key points in the manufacturing process of transistor devices. Since stress may be able to change the energy gap and the carrier mobility of silicon, it becomes an increasingly common method to improve the performance of a transistor by introducing a stress layer into the transistor. For example, a stress layer that can provide tensile stress is formed in an N-type transistor to improve the electron mobility, and a stress layer that can provide compressive stress is formed in an N-type transistor to improve the hole mobility.
However, according to existing fabrication methods, forming a plurality of plugs in a semiconductor structure that contains a stress layer may also cause damage to the stress layer, and thus may further lead to degraded performance of the formed semiconductor structure. The disclosed semiconductor structures and fabrication methods thereof are directed to solve one or more problems set forth above and other problems in the art.